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A power‐efficient 600‐mV pp voltage‐mode driver with independently matched pull‐up and pull‐down impedances
Author(s) -
Bae Woorham,
Jeong DeogKyoon
Publication year - 2015
Publication title -
international journal of circuit theory and applications
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.364
H-Index - 52
eISSN - 1097-007X
pISSN - 0098-9886
DOI - 10.1002/cta.2050
Subject(s) - swing , voltage , calibration , electrical impedance , cmos , impedance matching , power (physics) , electrical engineering , output impedance , electronic engineering , chip , engineering , physics , mechanical engineering , quantum mechanics
Summary In this study, a large‐swing, low‐power voltage‐mode driver with independently matched pull‐up and pull‐down impedances is proposed. To achieve large swing and constant impedances during a transition, a P‐over‐N structure is implemented with regulators calibrating the impedances. Two regulators are dedicated to matching the pull‐up and pull‐down impedances by regulating the supply voltages of the driver and predriver, respectively. Because background impedance calibration loops are adopted to track the process, voltage, and temperature (PVT) variations, the proposed driver can operate properly without additional calibration time. To reduce the power consumption of the calibration loops, scaled replicas of the actual driver are used. Moreover, an analysis of design optimization for the proposed driver is presented. The proposed driver was fabricated in 65‐nm CMOS technology and verified at a 5‐Gb/s data rate. Measurement results show that the proposed driver has a voltage swing of 600 mV pp and a horizontal eye opening of 0.5 UI. The prototype chip consumes 6 mW at a 1.0‐V supply. Copyright © 2014 John Wiley & Sons, Ltd.