A fast‐corrected all‐digital DCC with synchronous input clock

Summary This paper presents a fast‐corrected all‐digital duty‐cycle corrector (DCC) with synchronous input clock. The proposed DCC has many features, including fast locking in 4 cycles, wide range correction, and synchronous 50% duty‐cycle clock with an input clock. The circuit can operate from 500 to 900 MHz and corrects a wide range of input duty cycle ranging from 25 to 75%. The duty‐cycle error of the output clock is between −2.4 and 2.7%. The largest static phase error between the input and output clock is −44 ps at 900 MHz. The RMS and peak‐to‐peak jitters are 1.9 and 14.7 ps at 900 MHz, respectively. The proposed DCC is implemented in a 0.18‐µm complementary metal oxide semiconductor process. The proposed DCC occupies an area of 0.05 mm 2 and dissipates 23 mW with 1.8‐V supply voltage at 900 MHz. Copyright © 2014 John Wiley & Sons, Ltd.