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Multiplier‐less VLSI architectures for radix‐2 2 folded pipelined complex FFT core
Author(s) -
Mankar Abhishek,
Prasad N,
Das Ansuman DiptiSankar,
Meher Sukadev
Publication year - 2015
Publication title -
international journal of circuit theory and applications
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.364
H-Index - 52
eISSN - 1097-007X
pISSN - 0098-9886
DOI - 10.1002/cta.2038
Subject(s) - cordic , computer science , field programmable gate array , fast fourier transform , multiplier (economics) , very large scale integration , parallel computing , compiler , latency (audio) , arithmetic , computer hardware , embedded system , algorithm , mathematics , telecommunications , programming language , economics , macroeconomics
Summary The advantages of a multiplier‐less architecture are reduction in hardware and latency. This paper proposes multiplier‐less architectures for the implementation of radix‐2 2 folded pipelined complex FFT core based on coordinate rotation digital computer (CORDIC) and new distributed arithmetic (NEDA). The number of points considered in the work is sixteen and the folding is done by a factor of four. The proposed designs have been implemented on Xilinx XC5VSX240T‐2FF1738 FPGA and also have been synthesized using the Synopsys design compiler. Proposed designs based on NEDA have reduced area over 83% and based on CORDIC have a reduced area over 78%. The observed slice‐delay product for NEDA based designs are 2.196 and 5.735, and for CORDIC based design is 2.369. Copyright © 2014 John Wiley & Sons, Ltd.