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A design methodology for power‐efficient reconfigurable SC ΔΣ modulators
Author(s) -
Porrazzo S.,
Morgado A.,
San Segundo Bello D.,
Van Hoof C.,
Yazicioglu R. Firat,
Roermund A. H. M.,
Cantatore E.
Publication year - 2015
Publication title -
international journal of circuit theory and applications
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.364
H-Index - 52
eISSN - 1097-007X
pISSN - 0098-9886
DOI - 10.1002/cta.1992
Subject(s) - oversampling , capacitor , electronic engineering , bandwidth (computing) , computer science , transistor , integrator , engineering , electrical engineering , cmos , telecommunications , voltage
Summary This paper presents a methodology to design reconfigurable switched‐capacitor delta‐sigma modulators (ΔΣMs) capable of keeping their corresponding power efficiency figures constant and optimal for a set of resolutions and signal bandwidths. This method is especially suitable for low‐bandwidth, medium‐to‐high‐resolution specifications, which are common in biomedical application range. The presented methodology is based on an analytic model of all different contributions to the power dissipation of the ΔΣM. In particular, a novel way to predict the static power dissipated by integrators based on class A and class AB operational transconductance amplifier is presented. The power‐optimal solution is found in terms of filter order, quantizer resolution, oversampling ratio, and capacitor dimensions for a targeted resolution and bandwidth. As the size of the sampling capacitors is crucial to determine power consumption, three approaches to achieve reconfigurability are compared: sizing the sampling capacitors to achieve the highest resolution and keep them constant, change only the first sampling capacitor according to the targeted resolution, or program all sampling capacitors to the required resolution. The second approach results in the best trade‐off between power efficiency and simplicity. A reconfigurable ΔΣM for biomedical applications is designed at transistor level in a 0.18‐µm complementary metal–oxide–semiconductor process following the methodology discussed. A comparison between the power estimated by the proposed analytic model and the transistor implementation shows a maximum difference of 17%, validating thus the proposed approach. Copyright © 2014 John Wiley & Sons, Ltd.