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Noise‐tolerant dynamic CMOS circuits design by using true single‐phase clock latching technique
Author(s) -
Wey IChyn,
Chang ChunWei,
Liao YuCheng,
Chou HengJui
Publication year - 2015
Publication title -
international journal of circuit theory and applications
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.364
H-Index - 52
eISSN - 1097-007X
pISSN - 0098-9886
DOI - 10.1002/cta.1976
Subject(s) - adder , cmos , electronic engineering , electronic circuit , noise (video) , phase noise , computer science , dynamic demand , clock signal , electrical engineering , power (physics) , engineering , physics , quantum mechanics , artificial intelligence , image (mathematics)
Summary In this paper, a true‐single‐phase clock latching based noise‐tolerant (TSPCL‐NT) design for dynamic CMOS circuits is proposed. A TSPCL‐NT dynamic circuit can isolate and filter noise before the noise enters into the dynamic circuit. Therefore, it cannot only greatly enhance the noise tolerance of dynamic circuits but also release the signal contention between the feedback keeper and the pull‐down network effectively. As a result, noise tolerance of dynamic circuits can be improved with lower sacrifice in power consumption and operating speed. In the 16‐bit TSPCL‐NT Manchester adder, the average noise threshold energy can be enhanced by 3.41 times. In the meanwhile, the power‐delay product can be improved by 5.92% as compared with the state‐of‐the art 16‐bit XOR‐NT Manchester adder design under TSMC 90 nm CMOS process. Copyright © 2014 John Wiley & Sons, Ltd.