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A data aware 9T static random access memory cell for low power consumption and improved stability
Author(s) -
Singh Ajay Kumar,
Seong Mah Meng,
Prabhu C. M. R.
Publication year - 2014
Publication title -
international journal of circuit theory and applications
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.364
H-Index - 52
eISSN - 1097-007X
pISSN - 0098-9886
DOI - 10.1002/cta.1897
Subject(s) - computer science , memory cell , access time , power consumption , data retention , random access , noise margin , margin (machine learning) , power (physics) , standby power , noise (video) , transistor , reduction (mathematics) , electronic engineering , computer hardware , voltage , electrical engineering , computer network , engineering , mathematics , physics , geometry , computer security , quantum mechanics , machine learning , artificial intelligence , image (mathematics)
Reducing the power consumption in static random access memory can significantly improve the system power efficiency, reliability, and performance. In this paper, we propose a data aware static random access memory cell to reduce the power consumption during read and write operation. The proposed cell contains nine transistors with separate read/write ports. The write operation in the proposed cell is controlled by an additional write signal instead of word line. Because of isolation of the storage nodes with bit lines, read signal‐to‐noise margin is equal to ideal hold signal‐to‐noise margin of the conventional cell. The proposed cell saves approximately more than 43% active power compared with the 6T cell and other published cells. The proposed cell gives faster write access and low leakage current compared with the conventional and other cells. About 99% standby column power reduction, with 128 cells, is observed in the proposed cell. Copyright © 2013 John Wiley & Sons, Ltd.