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Towards minimum achievable phase noise of relaxation oscillators
Author(s) -
Geraedts Paul F. J.,
Tuijl Ed A. J. M.,
Klumperink Eric A. M.,
Wienk Gerard J. M.,
Nauta Bram
Publication year - 2014
Publication title -
international journal of circuit theory and applications
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.364
H-Index - 52
eISSN - 1097-007X
pISSN - 0098-9886
DOI - 10.1002/cta.1849
Subject(s) - phase noise , relaxation oscillator , noise (video) , limit (mathematics) , figure of merit , physics , phase locked loop , oscillator phase noise , phase (matter) , capacitor , ring oscillator , electronic engineering , control theory (sociology) , cmos , computer science , noise figure , voltage controlled oscillator , engineering , optoelectronics , mathematics , quantum mechanics , mathematical analysis , amplifier , control (management) , voltage , artificial intelligence , image (mathematics)
A relaxation oscillator design is described, which has a phase noise rivaling ring oscillators, while also featuring linear frequency tuning. We show that the comparator in a relaxation‐oscillator loop can be prevented from contributing to 1/f 2 colored phase noise and degrading control linearity. The resulting oscillator is implemented in a power efficient way with a switched‐capacitor circuit. The design results from a thorough analysis of the fundamental phase noise contributions. Simple expressions modeling the theoretical phase noise performance limit are presented, as well as a design strategy to approach this limit. To verify theoretical predictions, a relaxation oscillator is implemented in a baseline 65 nm CMOS process, occupying 200 µm × 150 µm. Its frequency tuning range is 1–12 MHz, and its phase noise is L(100kHz) = −109dBc/Hz at f osc = 12MHz, while consuming 90 μW. A figure of merit of −161dBc/Hz is achieved, which is only 4 dB from the theoretical limit. Copyright © 2012 John Wiley & Sons, Ltd.