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Gate‐level body biasing technique for high‐speed sub‐threshold CMOS logic gates
Author(s) -
Corsonello P.,
Lanuzza M.,
Perri S.
Publication year - 2014
Publication title -
international journal of circuit theory and applications
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.364
H-Index - 52
eISSN - 1097-007X
pISSN - 0098-9886
DOI - 10.1002/cta.1838
Subject(s) - nand gate , nor gate , logic gate , cmos , pass transistor logic , and or invert , gate equivalent , threshold voltage , biasing , electronic engineering , electronic circuit , transistor , computer science , and gate , electrical engineering , or gate , energy (signal processing) , voltage , engineering , mathematics , gate oxide , statistics
An efficient technique for designing high‐performance logic circuits operating in sub‐threshold region is proposed. A simple gate‐level body biasing circuit is exploited to change dynamically the threshold voltage of transistors on the basis of the gate status. Such an auxiliary circuit prepares the logic gate for fast switching while maintaining energy efficiency. If 200 aJ is the target total energy per operation consumption, a two input NAND (NOR) gate designed as described here shows a delay reduction between 20% (16%) and 40% (48%), with respect to previously proposed sub‐threshold approaches. Copyright 2012 John Wiley & Sons, Ltd.