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Reconfigurable architecture of VDF filter for multidimensional data
Author(s) -
Atitallah Ahmed Ben,
Boudabous Anis,
Khriji Lazhar,
Masmoudi Nouri
Publication year - 2013
Publication title -
international journal of circuit theory and applications
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.364
H-Index - 52
eISSN - 1097-007X
pISSN - 0098-9886
DOI - 10.1002/cta.1815
Subject(s) - field programmable gate array , computer science , context (archaeology) , microprocessor , filter (signal processing) , computer hardware , process (computing) , noise (video) , reconfigurable computing , component (thermodynamics) , hardware architecture , embedded system , computer architecture , image (mathematics) , software , artificial intelligence , paleontology , physics , thermodynamics , computer vision , biology , programming language , operating system
In this paper, we present a hardware reconfigurable architecture of vector directional filter (VDF) and an experimental validation based on HW/SW implementation context. An FPGA with a Nios II processor combines the benefits of a programmable logic component as well as a microprocessor. VDF is very useful in multidimensional data (such as color images) for noise removal and details preservation. Comparative results between simulations of ANSI‐C and hardware implementation are given. An estimate method of nonlinear function is presented and serves as an approximation for the appropriate hardware implementation on FPGA. Finally, to verify the functionality of the implementation, a validation state using FPGA platform has been performed. This validation demonstrated that our implementation hardware system speeds up the filtering process as well as preserving a high data quality (image quality). Copyright © 2012 John Wiley & Sons, Ltd.