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Fault‐tolerant programmable logic array for nanoelectronics
Author(s) -
Flak Jacek,
Laiho Mika
Publication year - 2012
Publication title -
international journal of circuit theory and applications
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.364
H-Index - 52
eISSN - 1097-007X
pISSN - 0098-9886
DOI - 10.1002/cta.1795
Subject(s) - redundancy (engineering) , programmable logic array , computer science , programmable logic device , nanoelectronics , logic gate , fault tolerance , programmable logic controller , macrocell array , embedded system , simple programmable logic device , field programmable gate array , computer architecture , logic synthesis , logic family , electronic engineering , engineering , distributed computing , algorithm , materials science , nanotechnology , operating system
SUMMARY This paper presents the architecture for a nanoelectronic logic system in which a regular array of logic gates with programmable interconnections is accompanied by a data transmitter and receiver as well as program registers and a controller. Binary programmable interconnections assure system versatility by providing the means of computing different logic operations. They also allow setting the redundancy level via the number of columns clustered to compute a certain function. A system operation is explained and visualized with a number of examples. The embedded scheme of fault tolerance can effectively mitigate permanent, as well as transient, faults. Some implementation and performance aspects are approached through simulations of single‐electron tunneling structures. However, the proposed architectural concept is generic and can be applied to systems implemented with alternative nanotechnologies. Copyright © 2012 John Wiley & Sons, Ltd.