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Compact CMOS implementation of a low‐power, current‐mode programmable cellular neural network
Author(s) -
Ravezzi L.,
Dalla Betta G.F.,
Setti G.
Publication year - 2001
Publication title -
international journal of circuit theory and applications
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.364
H-Index - 52
eISSN - 1097-007X
pISSN - 0098-9886
DOI - 10.1002/cta.147
Subject(s) - cmos , computer science , realization (probability) , cellular neural network , chip , computer hardware , electronic engineering , artificial neural network , computer architecture , topology (electrical circuits) , embedded system , electrical engineering , engineering , artificial intelligence , telecommunications , statistics , mathematics
Abstract We report on the design and characterization of a full‐analog programmable current‐mode cellular neural network (CNN) in CMOS technology. In the proposed CNN, a novel cell‐core topology, which allows for an easy programming of both feedback and control templates over a wide range of values, including all those required for many signal processing tasks, is employed. The CMOS implementation of this network features both low‐power consumption and small‐area occupation, making it suitable for the realization of large cell‐grid sizes. Device level and Monte Carlo simulations of the network proved that the proposed CNN can be successfully adopted for several applications in both grey‐scale and binary image processing tasks. Results from the characterization of a preliminary CNN test‐chip (8×1 array), intended as a simple demonstrator of the proposed circuit technique, are also reported and discussed. Copyright © 2001 John Wiley & Sons, Ltd.