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Deposition pressure influence on morphological and electrical properties of poly‐silicon
Author(s) -
Sciuto M.,
Papalino L.,
Gagliano C.,
Padalino M.,
Coccorese C.,
Mello D.,
Renna G.,
Franco G.
Publication year - 2005
Publication title -
crystal research and technology
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.377
H-Index - 64
eISSN - 1521-4079
pISSN - 0232-1300
DOI - 10.1002/crat.200410466
Subject(s) - materials science , electrical resistivity and conductivity , silicon , grain size , amorphous solid , deposition (geology) , crystallization , layer (electronics) , amorphous silicon , composite material , shrinkage , nanotechnology , chemical engineering , crystalline silicon , metallurgy , crystallography , chemistry , electrical engineering , geology , paleontology , sediment , engineering
In the modern MOS‐based device the poly‐silicon morphological and electrical properties play a very important role for the final die performance. In particular for flash memory devices, due to the continuous shrinkage, it is very important to control the relationship between process parameters and layer characteristics. In this paper we discuss the influence of deposition pressure on morphological and electrical properties of poly‐silicon deposited by LPCVD. We show that, in spite of amorphous state of as‐deposited layer, after crystallization, poly‐silicon grain size, resistivity and work function strongly depend on deposition pressure. TEM plane view with grain size distribution of the three more interesting cases has been studied. Then these grain sizes have been related with the resistivity. It has been observed that higher pressure tends to decrease grain size and resistivity while lower pressure has the opposite effect. Finally AFM analysis has been performed in order to determine a qualitative grain distribution on the surface. (© 2005 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)