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Design of time‐interleaved data acquisition system based on Network on Chip
Author(s) -
Zhao Jiangwei,
Xu Chuanpei
Publication year - 2021
Publication title -
concurrency and computation: practice and experience
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.309
H-Index - 67
eISSN - 1532-0634
pISSN - 1532-0626
DOI - 10.1002/cpe.6180
Subject(s) - data acquisition , computer science , timestamp , scalability , gigabit ethernet , router , embedded system , computer hardware , ethernet , data transmission , real time computing , computer network , database , operating system
In order to solve the existing problems of time‐interleaved data acquisition system's poor scalability, limited acquisition channels, and complicated clock system based on System on Chip(SoC), this work presents a novel method of high‐speed data acquisition based on Network on Chip (NoC) communication architecture and time‐interleaved principle. Six analog‐to‐digital data acquisition resource nodes are hooked up to the NoC according to the unified features of NoC router interface. The data acquisition controller controls the time‐interleaved acquisition's timing sequences and realizes the remote transmission of data through two Gigabit Ethernet resource nodes. Adding timestamp to the collected data of each channel can recover the waveform signal accurately. The experiment results show that the combination of NoC communication architecture and time‐interleaved data acquisition has a certain innovative significance.