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A high‐performance FPGA‐based multicrossbar prioritized network‐on‐chip
Author(s) -
Alaei Mohammad,
Yazdanpanah Fahimeh
Publication year - 2020
Publication title -
concurrency and computation: practice and experience
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.309
H-Index - 67
eISSN - 1532-0634
pISSN - 1532-0626
DOI - 10.1002/cpe.6055
Subject(s) - router , field programmable gate array , reconfigurability , embedded system , network on a chip , computer science , fpga prototype , computer architecture , latency (audio) , computer hardware , computer network , telecommunications
Summary High performance system‐on‐chip (SoCs) designs have led to high‐density integrated circuits using field programmable gate arrays (FPGAs) for rapid prototyping and reconfigurable digital circuits. Using FPGA reconfigurability, it is possible to design a configurable network‐on‐chip (NoC) for different applications. NoC architectures provide efficient communication infrastructures for implementing very large SoCs. In this article, we propose HiFMP, a high‐performance FPGA‐based multicrossbar prioritized NoC router. The aim followed by the proposed router is designing a low‐power NoC router with high performance in terms of energy‐efficiency, network throughput, area, and latency for efficient FPGA realization. HiFMP is a parameterizable router, and is effectively used for an FPGA‐based NoC with mesh topology. Performance evaluations include network‐level analysis and hardware exploration; the results demonstrate the effectiveness and high performance of HiFMP in terms of latency, throughput, power consumption, and area, comparing with the existing related architectures.