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On‐chip evolution of combinational logic circuits using an improved genetic‐simulated annealing algorithm
Author(s) -
Shang Qianyi,
Chen Lijun,
Peng Peng
Publication year - 2020
Publication title -
concurrency and computation: practice and experience
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.309
H-Index - 67
eISSN - 1532-0634
pISSN - 1532-0626
DOI - 10.1002/cpe.5486
Subject(s) - simulated annealing , algorithm , combinational logic , electronic circuit , computer science , genetic algorithm , convergence (economics) , chip , adaptive simulated annealing , field programmable gate array , logic gate , parallel computing , engineering , embedded system , telecommunications , machine learning , economic growth , electrical engineering , economics
Summary This paper presents the on‐chip evolution system of combinational logic circuits by a new hybrid algorithm known as improved genetic‐simulated annealing algorithm (IGASA). IGASA is based on the concept and principles of genetic algorithm (GA) and simulated annealing (SA). The main idea is to combine GA's global search ability with the advantage of SA's fast convergence to reach an optimal solution. In this paper, a new mutation operation and a repeated annealing (RA) process are introduced to overcome the premature convergence of the standard GA and the large number of searches in the later period. An elitist strategy to enhance convergence characteristic of the proposed algorithm is incorporated to better speed up the evolution process. In addition, the new algorithm is implemented in a new evolvable platform using Intel Cyclone V FPGA with an embedded ARM microprocessor. Comparison of the performance of the improved algorithm to the pure GASA algorithm and standard GA is presented on a number of case studies. The experiment results demonstrate that feasible circuits are always achieved by the IGASA algorithm unlike with other algorithms and the number of generations required is less.