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Universal gates on garbled circuit construction
Author(s) -
Innocent A. Anasuya Threse,
K Sangeeta,
Prakash G.
Publication year - 2019
Publication title -
concurrency and computation: practice and experience
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.309
H-Index - 67
eISSN - 1532-0634
pISSN - 1532-0626
DOI - 10.1002/cpe.5236
Subject(s) - computer science , encryption , circuit extraction , computation , xor gate , algorithm , arithmetic , equivalent circuit , logic gate , mathematics , electrical engineering , engineering , computer network , voltage
Summary Efficient garbled circuit construction can lead to more practical secure computation protocols. Garbled circuit construction has been considered as a separate goal for optimization as efficiency of the secure computation protocol is directly related to the efficiency of garbled circuit construction. Various optimizations such as, point‐and‐permute technique, free‐XOR, garbled row reduction, and dual‐key cipher are proved to make the garbled circuit construction efficient. In this paper, we propose garbled circuit construction with the universal gates; for demonstration purpose, we have considered NOR gates and shown optimization on circuit construction in two models. By the use of single type of gate, the gate array in the circuit representation is eliminated and a constant value is used in protocols. In addition, we have reduced the number of rows in garbled table to two rows per gate with two or zero encryption calls during garbled circuit construction and two or zero decryption calls during evaluation of garbled circuit.