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An efficient model for quantifying the interaction between structural properties of software and hardware in the ARM big.LITTLE architecture
Author(s) -
Stepanovic Srboljub,
Georgakarakos Georgios,
Holmbacka Simon,
Lilius Johan
Publication year - 2019
Publication title -
concurrency and computation: practice and experience
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.309
H-Index - 67
eISSN - 1532-0634
pISSN - 1532-0626
DOI - 10.1002/cpe.5230
Subject(s) - computer science , software , workload , multi core processor , cache , selection (genetic algorithm) , core (optical fiber) , parallel computing , metric (unit) , architecture , distributed computing , computer architecture , operating system , artificial intelligence , engineering , art , telecommunications , operations management , visual arts
Summary Heterogeneous architectures offer the opportunity to achieve high performance and energy efficiency by selecting appropriate cores for the execution of ever‐changing software applications. Appropriate core selection depends on the interaction between the structural properties of the software and the hardware that influences the performance of the software. We propose a model for efficient core selection when executing software on ARM's big.LITTLE heterogeneous architecture. It features a metric based on the correlation between the performance and the number of last‐level data cache (LLC) misses on a big and a LITTLE core. Additionally, our model defines a soft threshold in terms of the number of LLC misses, which determines efficient core selection. We verify the model using stress and variable workload benchmarks as well as two popular high‐throughput applications for mutlicore targets, namely, HEVC and LDPC decoders, profiled with X‐Mem, Linux perf, and PMCTrack dynamic tools. Results show that our model can be used for efficient core selection with a relatively small error probability.