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A Novel Architecture of Modified Turbo Codes with an area efficient high speed interleaver
Author(s) -
Ilango Poonguzhali,
Chokkalingam Arun
Publication year - 2018
Publication title -
concurrency and computation: practice and experience
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.309
H-Index - 67
eISSN - 1532-0634
pISSN - 1532-0626
DOI - 10.1002/cpe.5067
Subject(s) - turbo code , computer science , encoder , serial concatenated convolutional codes , algorithm , convolutional code , bit error rate , decoding methods , concatenated error correction code , bcjr algorithm , electronic engineering , block code , engineering , operating system
Summary Modified Turbo Codes (MTC) is preferred over conventional Turbo Convolutional Codes (TCC) as they provide nearly the same performance but with the additional benefit of reduced decoding complexity. The Improved Low Complexity Hybrid Turbo Codes (ILCHTC) is a type of MTC, which achieves a Bit Error Rate (BER) performance near to Shannon's limit. This paper presents a high speed novel encoder structure called Enhanced ILCHTC and a high speed low power novel interleaver for the MTC and analyzes its BER performance. From the simulation results, it is observed that BER performance of Enhanced ILCHTC and ILCHTC with proposed interleaver is better and has high degree of error convergence and requires less than 50% of computations than TCC. From the synthesized results, it is observed that the computation time required to shuffle the bits by the proposed interleaver is 7.4% less than the time required by the existing interleaver. In addition, it is observed that the number of logic elements utilized by the proposed interleaver is 95, which is 8% less than the number of logic elements, utilized by the existing interleaver but the tradeoff is power, which is 1.63% more when compared to the existing interleaver. Thus, a high speed area efficient interleaver is proposed along with a novel encoder structure.