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An area‐efficient FFT processor for the OFDMA transceiver communication system
Author(s) -
Nirmala N.,
Sumathi S.
Publication year - 2018
Publication title -
concurrency and computation: practice and experience
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.309
H-Index - 67
eISSN - 1532-0634
pISSN - 1532-0626
DOI - 10.1002/cpe.4875
Subject(s) - orthogonal frequency division multiplexing , computer science , fast fourier transform , transceiver , electronic engineering , multiplexing , channel (broadcasting) , modulation (music) , frequency division multiplexing , wireless , computer hardware , computer network , telecommunications , engineering , algorithm , philosophy , aesthetics
Summary Orthogonal frequency division multiplexing (OFDM) is a well‐organized multiplexing scheme, which is long‐established in recent wireless and communication standards. OFDM resembles a system of exchanging information done with a nonflat channel called Discrete Multi‐Tone modulation (DMT) and Coded OFDM (COFDM). The data stream in this frequency modulation is divided across narrowband channels to limit interference and crosstalk. One of the extreme needs of OFDM is reasonable to be straight mean while sending and receiving systems. OFDM is extremely preferred for rapid data transmission and radio access method. In this paper, OFDM transceiver is carried out and implemented on FPGA. In addition, 128‐point IFFT/FFT pipelined architecture is proposed with the aim of optimizing area, frequency, and circuit complexity.