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An area‐efficient low‐power SCM topology for high performance network‐on Chip (NoC) architecture using an optimized routing design
Author(s) -
Poovendran R.,
Sumathi S.
Publication year - 2018
Publication title -
concurrency and computation: practice and experience
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.309
H-Index - 67
eISSN - 1532-0634
pISSN - 1532-0626
DOI - 10.1002/cpe.4760
Subject(s) - modelsim , computer science , network on a chip , verilog , router , interconnection , architecture , routing (electronic design automation) , mesh networking , network architecture , power (physics) , embedded system , network topology , topology (electrical circuits) , chip , computer architecture , computer network , field programmable gate array , engineering , vhdl , telecommunications , electrical engineering , wireless , art , physics , quantum mechanics , visual arts
Summary The incorporation of network‐on‐Chip with communication delivers a strengthening solution to the rising complexity and problems in system‐on‐chip. Here, mesh topology is shortly connected, utilizing the symmetric properties of the network, and is introduced. In addition, 4x4‐Router Architecture–Carry Select Adder (4x4‐RA‐CSLA) method is proposed to improve the function of the Router Architecture (RA) in the network. These features make the system achieve efficient architecture in terms of lower area and power for the interconnection of network scenarios. This new architecture is debugged using ModelSim with Verilog code. The experimental result shows improvement in area and power.