Premium
Energy efficient low‐power full‐adder by 65 nm CMOS technology in ALU
Author(s) -
N Suresh Kumar,
K Paramasivam
Publication year - 2018
Publication title -
concurrency and computation: practice and experience
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.309
H-Index - 67
eISSN - 1532-0634
pISSN - 1532-0626
DOI - 10.1002/cpe.4741
Subject(s) - adder , power–delay product , cmos , computer science , schematic , electronic engineering , logic gate , very large scale integration , pass transistor logic , power (physics) , efficient energy use , domino logic , transistor , logic synthesis , electrical engineering , computer hardware , logic family , engineering , embedded system , voltage , physics , quantum mechanics
Summary The arrangement of energy efficient low‐power full adder has vital role in VLSI systems. In this paper Energy Efficient Low‐power 9T full‐adder is proposed. Its functioning basis of Power Delay Product (PDP), Delay, power and area is distinguished in accordance with that current 1 bit full‐adder simulated by utilizing various Complementary MOS logic designs. Output provides an average minimization of 99.28% in power usage, 67.87% in area, 99.89% in delay, and 99.99% in Power‐Delay Product (PDP) distinguished to the traditional 28 Transistors CMOS logic. The ALU design has been implemented using 9T full adder. These logic gates are analysis at 65 nm technology of CMOS by utilizing Schematic Editor Tool.