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Evaluating the networking characteristics of the Cray XC‐40 Intel Knights Landing‐based Cori supercomputer at NERSC
Author(s) -
Doerfler Douglas,
Austin Brian,
Cook Brandon,
Deslippe Jack,
Kandalla Krishna,
Mendygral Peter
Publication year - 2017
Publication title -
concurrency and computation: practice and experience
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.309
H-Index - 67
eISSN - 1532-0634
pISSN - 1532-0626
DOI - 10.1002/cpe.4297
Subject(s) - xeon phi , supercomputer , xeon , computer science , parallel computing , suite , vectorization (mathematics) , operating system , computation , programming language , archaeology , history
Summary There are many potential issues associated with deploying the Intel Xeon Phi TM (code named Knights Landing [KNL]) manycore processor in a large‐scale supercomputer. One in particular is the ability to fully utilize the high‐speed communications network, given that the serial performance of a Xeon Phi TM core is a fraction of a Xeon®core. In this paper, we take a look at the trade‐offs associated with allocating enough cores to fully utilize the Aries high‐speed network versus cores dedicated to computation, eg, the trade‐off between MPI and OpenMP. In addition, we evaluate new features of Cray MPI in support of KNL, such as internode optimizations. We also evaluate one‐sided programming models such as Unified Parallel C. We quantify the impact of the above trade‐offs and features using a suite of National Energy Research Scientific Computing Center applications.