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Exploiting performance, dynamic power and energy scaling in full‐system simulators
Author(s) -
Duenha Liana,
Madalozzo Guilherme,
Moraes Fernando Gehm,
Azevedo Rodolfo
Publication year - 2016
Publication title -
concurrency and computation: practice and experience
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.309
H-Index - 67
eISSN - 1532-0634
pISSN - 1532-0626
DOI - 10.1002/cpe.4034
Subject(s) - frequency scaling , mpsoc , computer science , energy consumption , embedded system , design space exploration , multiprocessing , system on a chip , throughput , efficient energy use , workload , power (physics) , voltage , energy (signal processing) , parallel computing , engineering , operating system , electrical engineering , statistics , physics , mathematics , quantum mechanics , wireless
Summary Energy consumption constraints have become a critical issue in Multiprocessor Systems on Chip (MPSoC) designs. Whereas processor performance comes with a high power cost, there is an increasing interest in exploring the trade‐off between power and performance, taking into account the target application domain. Dynamic Voltage and Frequency Scaling (DVFS) techniques adaptively scale frequency or voltage level of CPU allowing it to reach just enough performance to process the system workload while meeting throughput constraints, and thereby, reducing the energy consumption. To explore this wide design space for energy efficiency and performance, hardware and software components, a system‐level simulation infrastructure must provide features to evaluate power savings mechanisms in early stages of the design. This paper presents an extension work of a framework for MPSoCs designs to support DVFS in MPSoCs simulators and evaluates three DVFS mechanisms. Our experiments show that applying DVFS in the system can save power and energy consumption, with negligible loss of performance. Copyright © 2016 John Wiley & Sons, Ltd.