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Efficient bit‐parallel subcircuit extraction using CUDA
Author(s) -
Hung CheLun,
Lin ChunYuan,
Ou ChiaShin,
Tseng YuanHong,
Hung PoYen,
Li ShipPeng,
Fu ChunTing
Publication year - 2016
Publication title -
concurrency and computation: practice and experience
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.309
H-Index - 67
eISSN - 1532-0634
pISSN - 1532-0626
DOI - 10.1002/cpe.3732
Subject(s) - cuda , computation , computer science , parallel computing , extraction (chemistry) , throughput , bit (key) , scale (ratio) , parallel processing , transistor , wafer , integrated circuit , computational science , algorithm , computer hardware , engineering , chemistry , chromatography , electrical engineering , telecommunications , physics , quantum mechanics , wireless , computer security , voltage , operating system
Summary Wafer processing technology has been improving rapidly. Moore's law has been exceeded as the number of transistors in a dense integrated circuit, now increases threefold or more, approximately every year. The integrated circuit has gone from very large scale to giga large scale. The extraction of subcircuits has therefore become computation‐intensive. In this paper, we propose an efficient bit‐parallel subcircuit extraction algorithm using graphic processing units. We conducted experimental trials and demonstrated that the proposed algorithm can achieve high throughput, suggesting practical applications in the extraction of subcircuits. Copyright © 2015 John Wiley & Sons, Ltd.