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STAC‐A2 on Intel architecture: evolving from scalar code to heterogeneous applications
Author(s) -
Fiksman Evgeny,
Nikolaev Andrey,
Burylov Ilya,
Salahuddin Sania
Publication year - 2015
Publication title -
concurrency and computation: practice and experience
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.309
H-Index - 67
eISSN - 1532-0634
pISSN - 1532-0626
DOI - 10.1002/cpe.3691
Subject(s) - xeon phi , xeon , computer science , benchmark (surveying) , parallel computing , coprocessor , pentium , operating system , single chip cloud computer , mmx , code (set theory) , programming language , cloud computing , set (abstract data type) , geodesy , cloud testing , cloud computing security , geography
Summary STAC‐A2™ is a compute and memory intensive industry benchmark in the field of market risk analysis. The benchmark specifications were created by the Securities Technology Analysis Center (STAC®), and are based on the inputs collected from the leading trading companies, universities, and high performance computing vendors. The specifications describe models that represent realistic market risk analysis workloads. In this paper, we discuss the development steps that lead to the competitive performance of the STAC‐A2 benchmark executed on systems consisting of Intel® Xeon® processors and an Intel® Xeon Phi™ coprocessor. We show the importance of the utilization of all parallel resources available on Intel architectures to achieve maximum performance. We demonstrate that the offload extension supported by Intel® Composer XE minimizes the efforts required to create accelerated applications by using only C/C++ language. With Intel's latest implementation of the STAC‐A2 benchmark, we were able to achieve a significant (800%) performance gain by using a heterogeneous approach running on two Intel Xeon E5‐2699 v3 processors and a single Intel® Xeon Phi™ 7120A card, compared with earlier version running on only two Intel Xeon E5‐2697 v2 processors. Copyright © 2016 John Wiley & Sons, Ltd.