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A real‐time capable coherent data cache for multicores
Author(s) -
Pyka Arthur,
Rohde Mathias,
Uhrig Sascha
Publication year - 2013
Publication title -
concurrency and computation: practice and experience
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.309
H-Index - 67
eISSN - 1532-0634
pISSN - 1532-0626
DOI - 10.1002/cpe.3172
Subject(s) - computer science , cache coherence , cache , mesi protocol , bottleneck , multi core processor , scalability , cache invalidation , bus sniffing , cache algorithms , parallel computing , cache pollution , coherence (philosophical gambling strategy) , cpu cache , distributed computing , embedded system , operating system , physics , quantum mechanics
SUMMARY In multicore systems, the concurrent access to shared data generates a bottleneck for the system performance. Cache coherence techniques have been introduced to enable fast access while preserving the data coherence, but these coherence protocols are critical in hard real‐time systems. Because the frequent inter‐cache communication leads to unpredictable interferences between the cores, the system's timing behaviour is hard to analyse. In this paper, we propose a new, hard real‐time capable strategy for multicore systems called on‐demand coherent cache (ODC 2 ). The technique is based on marginal hardware extensions compared with noncoherent caches and the use of common synchronisation techniques. ODC 2 provides coherent accesses to cached shared data as well as caching of private data. Because the presented strategy does not induce interferences between local caches, ODC 2 is capable for hard real‐time systems. We present an evaluation of performance and scalability of ODC 2 compared with two standard coherence protocols using a bus‐based multicore system. Copyright © 2013 John Wiley & Sons, Ltd.