Premium
Instruction scheduling and transformation for a VLIW unified reduced instruction set computer/digital signal processor processor with shared register architecture
Author(s) -
Lee ChengYu,
Hung MinChin,
Chang RongGuey
Publication year - 2014
Publication title -
concurrency and computation: practice and experience
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.309
H-Index - 67
eISSN - 1532-0634
pISSN - 1532-0626
DOI - 10.1002/cpe.2954
Subject(s) - very long instruction word , processor register , computer science , application specific instruction set processor , digital signal processor , instruction set , computer architecture , instruction scheduling , processor design , media processor , register file , parallel computing , scheduling (production processes) , pipeline burst cache , architecture , register allocation , digital signal processing , computer hardware , operating system , memory address , semiconductor memory , dynamic priority scheduling , compiler , cpu cache , schedule , engineering , two level scheduling , art , operations management , cache , visual arts , cache coloring
SUMMARY The popularity of multimedia applications made them a major theme in embedded systems. The key component for supporting multimedia application well is embedded processor. Thus, we have designed and implemented an embedded processor, called UniDual processor, to achieve this objective. Its key features are the integration of instructions of reduced instruction set computers (RISCs) and digital signal processors (DSPs) as well as the support of special instruction set and shared‐based clustered register architecture. However, an important issue of UniDual that remains open is how to efficiently allocate registers. In this paper, we present a scheduling and instruction transformation approach to resolve the aforementioned issue. The proposed approach schedules instructions and then transforms overlapped instructions into RISC and DSP instructions by taking communication overhead and hardware limitations into account. Compared with the greedy approach, the evaluation shows that our work is relatively effective in performance and code size reduction. Copyright © 2012 John Wiley & Sons, Ltd.