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NIC‐assisted cache‐efficient receive stack for message passing over Ethernet
Author(s) -
Goglin Brice
Publication year - 2011
Publication title -
concurrency and computation: practice and experience
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.309
H-Index - 67
eISSN - 1532-0634
pISSN - 1532-0626
DOI - 10.1002/cpe.1632
Subject(s) - computer science , ethernet , cache , queue , network interface controller , computer network , firmware , stack (abstract data type) , network packet , protocol stack , parallel computing , operating system , embedded system
High‐speed networking in clusters usually relies on advanced hardware features in the NICs, such as zero‐copy capability. Open‐MX is a high‐performance message‐passing stack tailored for regular Ethernet hardware without such capabilities. We present the addition of a multiqueue support in the Open‐MX receive stack so that all incoming packets for the same process are handled on the same core. We then introduce the idea of binding the target end process near its dedicated receive queue. This model leads to a more cache‐efficient receive stack for Open‐MX. It also proves that very simple and stateless hardware features may have a significant impact on message‐passing performance over Ethernet. The implementation of this model in a firmware reveals that it may not be as efficient as some manually tuned micro‐benchmarks. But our multiqueue receive stack generally performs better than the original single queue stack, especially on large communication patterns where multiple processes are involved and manual binding is difficult. Copyright © 2010 John Wiley & Sons, Ltd.