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Evolvable hardware design based on a novel simulated annealing in an embedded system
Author(s) -
He Guoliang,
Xiong Naixue,
Yang Laurence T.,
Kim Taihoon,
Hsu Ching Hsien,
Li Yuanxiang,
Hu Ting
Publication year - 2010
Publication title -
concurrency and computation: practice and experience
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.309
H-Index - 67
eISSN - 1532-0634
pISSN - 1532-0626
DOI - 10.1002/cpe.1604
Subject(s) - evolvable hardware , computer science , field programmable gate array , scalability , simulated annealing , digital electronics , computer architecture , electronic circuit , circuit design , computer engineering , embedded system , algorithm , engineering , electrical engineering , database
SUMMARY The auto‐design of electronic circuits for the next generation Information Technology (IT) computing environments is currently one of the most extensively studied issues in the field of evolvable hardware (EHW) architectures. It aims to improve the reliability and fault‐tolerance of hardware systems using embedded techniques. As the scalability of logic circuits becomes larger and more complex nowadays, its auto‐design is more and more difficult. In order to improve the efficiency and the capability of digital circuit auto‐design, in this paper, a multi‐objective simulated annealing (MSA)‐based increasable evolution approach is proposed in an embedded system. First, an extended matrix encoding method is used to indicate the potential performance of a circuit. Therefore, the risk of deleting a circuit with a good developing potential during evolution can be reduced. Second, we consider each output of a digital circuit as an objective, and MSA is designed for digital logic circuits with gradual evolution scheme. In the process of evolution, each objective is evolved in parallel with adaptive mechanism of neighborhood and a performance evaluation. Finally, a framework of online evolution with macro‐blocks is employed to implement MSA on a field‐programmable gate array efficiently and securely. In our experiments, six arithmetic circuits are designed to assess the performance of MSA with gate‐level and function‐level approaches comparing to other algorithms. The comparison results show that our method is very efficient in the auto‐design of EHW. Copyright © 2010 John Wiley & Sons, Ltd.