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Communicating process architecture for multicores
Author(s) -
May D.
Publication year - 2010
Publication title -
concurrency and computation: practice and experience
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.309
H-Index - 67
eISSN - 1532-0634
pISSN - 1532-0626
DOI - 10.1002/cpe.1434
Subject(s) - computer science , computer architecture , multi core processor , compiler , control reconfiguration , embedded system , process (computing) , process migration , architecture , variety (cybernetics) , instruction set , set (abstract data type) , parallel computing , operating system , programming language , art , artificial intelligence , visual arts
Communicating process architecture can be used to build efficient multicore chips scaling to hundreds of processors. Concurrent processing, communications and input–output are supported directly by the instruction set of the cores and by the protocol used in the on‐chip interconnect. Concurrent programs are compiled directly to the chip exploiting novel compiler optimizations. The architecture supports a variety of programming techniques, ranging from statically configured process networks to dynamic reconfiguration and mobile processes. Copyright © 2007 D. May.