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A “learning by design” application for modeling, implementing, and evaluating hardware architectures for artificial neural networks at undergraduate level
Author(s) -
GuzmánRamírez Enrique,
Garcia Ivan,
GarcíaJuárez Magdiel
Publication year - 2019
Publication title -
computer applications in engineering education
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.478
H-Index - 29
eISSN - 1099-0542
pISSN - 1061-3773
DOI - 10.1002/cae.22148
Subject(s) - computer science , artificial neural network , modular design , process (computing) , field (mathematics) , artificial intelligence , computer architecture , software , set (abstract data type) , multilayer perceptron , perceptron , software engineering , machine learning , programming language , mathematics , pure mathematics
Artificial intelligence is currently playing an important role in engineering education. Artificial neural networks (ANNs), for example, are one of the most important topics in computer science and computer engineering curricula. The teaching of ANNs, however, is challenging and current efforts are mainly focused on providing computer systems and/or software simulators to enhance results. In the present study, we introduce a field programmable gate array‐based educational system focused on the modeling, implementation, and evaluation of hardware architectures of ANNs type Multilayer Perceptron. The system was designed by taking into account the learning by design approach to creating a modular proposal, which is composed of a set of predefined modules that describe the behavior of each element of an ANN. This feature allows various neural architectures to be easily defined and to be applied to different specific problems. The system helps the teaching‐learning process by providing a design environment where undergraduate students can apply the knowledge acquired in lecture‐based courses related to areas, such as pattern recognition and neural networks. The experimental results present the design and implementation of an ANN hardware architecture that solves the iris‐plant problem.