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Incorporating hardware and software features into a prediction model for processor‐system throughput
Author(s) -
Beg Azam,
Prasad PWC
Publication year - 2016
Publication title -
computer applications in engineering education
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.478
H-Index - 29
eISSN - 1099-0542
pISSN - 1061-3773
DOI - 10.1002/cae.21681
Subject(s) - computer science , benchmark (surveying) , compiler , throughput , software , instructions per cycle , metric (unit) , computer architecture , artificial neural network , microarchitecture , parallel computing , computer engineering , embedded system , computer hardware , central processing unit , artificial intelligence , operating system , operations management , geodesy , economics , wireless , geography
The cycle‐accurate simulation is a method for design space study of a processor system before it goes for the hardware implementation. Even though the simulations provide precise results about the system performance, the simulation times are exorbitantly high for practical systems. Therefore, an alternative is to use experimentally‐ developed models that tend to be faster than the aforementioned simulations. This is an extension to our previous work done in the area of neural network models for assessing the processor system throughput. In addition to hardware‐related parameters, the current work includes multiple software‐related parameters to better represent the dynamic behavior of programs. Consequently, the model provides higher accuracy estimates of a widely used performance metric (instructions per cycle) when tested with industry standard CPU benchmark programs. Potential uses of the model are compiler design and computer architecture research and teaching. © 2015 Wiley Periodicals, Inc. Comput Appl Eng Educ 24:169–179, 2016; View this article online at wileyonlinelibrary.com/journal/cae ; DOI 10.1002/cae.21681 .