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Employed VeriLite simulation to improve SOC design and verification
Author(s) -
Sung WenTsai,
Ou ShihChing,
Liu YuFeng,
Chen ChiaHao
Publication year - 2012
Publication title -
computer applications in engineering education
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.478
H-Index - 29
eISSN - 1099-0542
pISSN - 1061-3773
DOI - 10.1002/cae.20404
Subject(s) - computer science , field programmable gate array , embedded system , software , fpga prototype , functional verification , matlab , system on a chip , process (computing) , time to market , computer architecture , electronic system level design and verification , computer hardware , operating system , formal verification , algorithm
This study employed the VeriLite PC‐based FPGA platform to improve co‐design and co‐verification simulation for System‐on‐chip (SOC) design process in FPGA transactional level modeling. This VeriLite platform is a real‐time simulations system. It provided SMIMS powerful Software—VeriComm, VeriInstrument and software developer's kit (SDK), offers an incredible performance and improvement in time‐to‐market. In this investigation, the main advantages of the system allow designers to use tools such as FPGA, Matlab, and Real‐View SOC designers to perform. Users can import the input signals easily from PC into the user‐designed circuit on the FPGA of VeriLite and export the output signals to PC for observation. A powerful method is proposed that speeds up the ESL design time with a precise result. VeriLite can be an intuitive and easy to use environment provides to access the functionality of HDL simulation acceleration, IP verification, and HW/SW co‐verification. In this study, the propose method allows users to quickly develop a hardware–software co‐design/co‐verification environment finally. © 2010 Wiley Periodicals, Inc. Comput Appl Eng Educ 20: 374–382, 2012