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Learning computer architecture concepts with the FPGA‐based “Move” microprocessor
Author(s) -
Guštin Veselko,
Bulić Patricio
Publication year - 2006
Publication title -
computer applications in engineering education
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.478
H-Index - 29
eISSN - 1099-0542
pISSN - 1061-3773
DOI - 10.1002/cae.20072
Subject(s) - computer science , microprocessor , computer architecture , programmable logic device , architecture , central processing unit , reduced instruction set computing , instruction set , set (abstract data type) , logic synthesis , field programmable gate array , programmable logic array , embedded system , programmable array logic , logic family , logic gate , operating system , computer hardware , programming language , art , algorithm , visual arts
In this article we introduce the use of a programmable logic device (PLD) in an application‐oriented study as an example of designing a microprocessor based on reduced instruction set computer (RISC) architecture. Since the concept of an in‐system configurable logic circuit is becoming increasingly popular, we now use it for the purpose of logic design. We suggest that students use PLDs when constructing a central processing unit (CPU) with their own configured functions that are directly implemented in the logic. Such an approach could greatly increase the understanding of the architectural concept of the CPU. © 2006 Wiley Periodicals, Inc. Comput Appl Eng Educ 14: 135–141, 2006; Published online in Wiley InterScience (www.interscience.wiley.com); DOI 10.1002/cae.20072