Very‐Low‐Temperature Integrated Complementary Graphene‐Barristor‐Based Inverter for Thin‐Film Transistor Applications

Complementary graphene‐barristor‐based inverters using n‐type ZnO:N and p‐type dinaphtho‐[2,3‐b:2′,3′‐f]thieno[3,2‐b]thiophene semiconductor layers are fabricated at a maximum process temperature lower than 200 °C. The devices display on/off ratios greater than 10 4 . The transmittance of the device stack is higher than 80% at wavelengths larger than 470 nm. The complementary graphene‐barristor inverter exhibits a high gain (>8 at V DD = 2 V) by using a back‐gate structure, which allows for aggressive gate‐dielectric scaling. The potential performance of the inverter, as projected using experimental device parameters, shows that a very high voltage gain of over 70 and a low switching power consumption of below 10 nW can be achieved at V DD = 2 V and an equivalent oxide thickness of 1 nm. These performances are very promising for thin‐film transistor applications.