Open AccessImpact of Phase‐Change Memory Flicker Noise and Weight Drift on Analog Hardware Inference for Large‐Scale Deep Learning Networks
Author(s) -
Han Jin-Ping,
Rasch Malte J.,
Liu Zuoguang,
Solomon Paul,
Brew Kevin,
Cheng Kangguo,
Ok Injo,
Chan Victor,
Longstreet Michael,
Kim Wanki,
Bruce Robert L.,
Cheng Cheng-Wei,
Saulnier Nicole,
Narayanan Vijay
Publication year - 2022
Publication title -
advanced intelligent systems
Language(s) - English
Resource type - Journals
ISSN - 2640-4567
DOI - 10.1002/aisy.202100179
Subject(s) - flicker noise , noise (video) , computer science , flicker , artificial neural network , artificial intelligence , inference , deep learning , electronic engineering , noise figure , telecommunications , engineering , amplifier , bandwidth (computing) , image (mathematics) , operating system
The analog AI core concept is appealing for deep‐learning (DL) because it combines computation and memory functions into a single device. Yet, significant challenges such as noise and weight drift will impact large‐scale analog in‐memory computing. Here, effects of flicker noise and drift on large DL systems are explored using a new flicker‐noise model with memory, which preserves temporal correlations, including a flicker noise figure of merit (FOM)A rto quantify impacts on system performance. Flicker noise is characterized for G e 2 S b 2 T e 5(GST) based phase‐change memory (PCM) cells with a discovery of read‐noise asymmetry tied to shape asymmetry of mushroom cells. This experimental read polarity dependence is consistent with Pirovano's trap activation and defect annihilation model in an asymmetric GST cell. The impact of flicker noise and resistance drift of analog PCM synaptic devices on deep‐learning hardware is assessed for six large‐scale deep neural networks (DNNs) used for image classification, finding that the inference top‐1 accuracy degraded with the accumulated device flicker noise and drift as ∝A r × t wait, and ∝ t wait− ν, respectively, where ν is the drift coefficient. These negative impacts could be mitigated with a new hardware‐aware (HWA) (pre)‐training of the DNNs, which is applied before programming to the analog arrays.