Open AccessIn‐Memory Vector‐Matrix Multiplication in Monolithic Complementary Metal–Oxide–Semiconductor‐Memristor Integrated Circuits: Design Choices, Challenges, and Perspectives
Author(s) -
Amirsoleimani Amirali,
Alibart Fabien,
Yon Victor,
Xu Jianxiong,
Pazhouhandeh M. Reza,
Ecoffey Serge,
Beilliard Yann,
Genov Roman,
Drouin Dominique
Publication year - 2020
Publication title -
advanced intelligent systems
Language(s) - English
Resource type - Journals
ISSN - 2640-4567
DOI - 10.1002/aisy.202000115
Subject(s) - computer science , von neumann architecture , bottleneck , in memory processing , matrix multiplication , resistive random access memory , computer architecture , key (lock) , massively parallel , integrated circuit , memristor , context (archaeology) , supercomputer , crossbar switch , memory bandwidth , parallel computing , embedded system , electronic engineering , electrical engineering , engineering , search engine , computer security , voltage , query by example , quantum , biology , operating system , paleontology , quantum mechanics , information retrieval , web search query , physics , telecommunications
The low communication bandwidth between memory and processing units in conventional von Neumann machines does not support the requirements of emerging applications that rely extensively on large sets of data. More recent computing paradigms, such as high parallelization and near‐memory computing, help alleviate the data communication bottleneck to some extent, but paradigm‐shifting concepts are required. In‐memory computing has emerged as a prime candidate to eliminate this bottleneck by colocating memory and processing. In this context, resistive switching (RS) memory devices is a key promising choice, due to their unique intrinsic device‐level properties, enabling both storing and computing with a small, massively‐parallel footprint at low power. Theoretically, this directly translates to a major boost in energy efficiency and computational throughput, but various practical challenges remain. A qualitative and quantitative analysis of several key existing challenges in implementing high‐capacity, high‐volume RS memories for accelerating the most computationally demanding computation in machine learning (ML) inference, that of vector‐matrix multiplication (VMM), is presented. The monolithic integration of RS memories with complementary metal–oxide–semiconductor (CMOS) integrated circuits is presented as the core underlying technology. The key existing design choices in terms of device‐level physical implementation, circuit‐level design, and system‐level considerations is reviewed and an outlook for future directions is provided.