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High Electrical Anisotropic Multilayered Self‐Assembled Organic Films Based on Graphene Oxide and PEDOT:PSS
Author(s) -
Gaál Gabriel,
Braunger Maria Luisa,
Rodrigues Varlei,
Riul Antonio,
Gomes Henrique Leonel
Publication year - 2021
Publication title -
advanced electronic materials
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 2.25
H-Index - 56
ISSN - 2199-160X
DOI - 10.1002/aelm.202100255
Subject(s) - materials science , ambipolar diffusion , pedot:pss , graphene , anisotropy , polystyrene sulfonate , dielectric , field effect transistor , optoelectronics , charge carrier , electron mobility , transistor , nanotechnology , layer (electronics) , electron , voltage , electrical engineering , optics , physics , engineering , quantum mechanics
Multilayered self‐assembled structures having different constituents are very appealing for preparing novel materials with unusual electrical phenomena not observed on the individual sheets. Here, the fabrication and characterization of aligned multilayered architectures comprised of reduced graphene oxide (rGO) and poly(3,4‐ethylenedioxythiophene) polystyrene sulfonate (PEDOT:PSS), embedded into polymer electrolytes, are reported. The in‐plane conductivity is five orders of magnitude higher than the cross‐plane value, resulting in the highest anisotropic ratio reported to date for multilayer materials. Temperature‐dependent measurements corroborate the high anisotropic electrical behavior, with charge transport weakly thermally activated ( E a = 33 meV) along the aligned conductive phases. Cross‐plane charge transport fits well with the variable ranging hopping model, presenting an activation energy of 1.0 eV. Such a high anisotropic electrical behavior is explored in a novel transistor architecture where the anisotropic film operates simultaneously as a dielectric layer and as a transistor channel, with the cross‐plane electric field modulating the in‐plane conduction. The device shows ambipolar charge transport; however, the n‐type carrier transport dominates the conduction with the field‐effect mobility of 4.0 cm 2 V –1 s –1 . A simple and efficient way is presented to use electrical anisotropy to tailor transistors without a lattice mismatch at the dielectric/semiconductor interface.