Premium
Operation Principles of ZnO/Al 2 O 3 ‐AlDMP/ZnO Stacked‐Channel Ternary Thin‐Film Transistor
Author(s) -
Kim SoYoung,
Kim Kiyung,
Kim A. Reum,
Lee HoIn,
Lee Yongsu,
Kim SeungMo,
Yu Sung Ho,
Lee HaeWon,
Hwang Hyeon Jun,
Sung Myung Mo,
Lee Byoung Hun
Publication year - 2021
Publication title -
advanced electronic materials
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 2.25
H-Index - 56
ISSN - 2199-160X
DOI - 10.1002/aelm.202100247
Subject(s) - ternary operation , materials science , optoelectronics , noise margin , transistor , logic gate , voltage , threshold voltage , inverter , resistive touchscreen , electronic engineering , electrical engineering , computer science , engineering , programming language
For many decades, novel devices demonstrating step‐wise current–voltage characteristic at room temperature have been pursued to realize multi‐valued logic computing that has significant advantages such as extremely low power consumption and high‐density information‐processing capability. Recently, a novel ternary logic transistor has been constructed using an ultrathin ZnO/Al 2 O 3 ‐AlDMP/ZnO channel exhibiting a mobility edge‐quantized conduction for the intermediate current level. This study investigates the operation principle of the ternary device using ZnO/Al 2 O 3 ‐AlDMP/ZnO stack and concludes that the first ZnO layer controls the level of the intermediate current, while the second ZnO layer controls the threshold voltage of the ternary device. These controllable electrical properties of the intermediate state of the ternary device have been applied to an n‐type resistive‐load standard ternary inverter, demonstrating the feasibility to achieve a ternary logic circuit consuming extremely low power with an optimal noise margin.