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Efficient Parallel Multi‐Bit Logic‐in‐Memory Based on a Ultrafast Ferroelectric Tunnel Junction Memristor
Author(s) -
Ma Chao,
Tao Linfeng,
Luo Zhen,
Sun Haoyang,
Liu Chuanchuan,
Wang Zijian,
Zhou Xiang,
Jin Xi,
Yin Yuewei,
Li Xiaoguang
Publication year - 2021
Publication title -
advanced electronic materials
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 2.25
H-Index - 56
ISSN - 2199-160X
DOI - 10.1002/aelm.202000988
Subject(s) - memristor , von neumann architecture , adder , computer science , bottleneck , computation , parallel computing , logic gate , binary number , computer hardware , electronic engineering , arithmetic , algorithm , embedded system , cmos , mathematics , engineering , operating system
Memristive logic‐in‐memory (LIM) is an attractive candidate for in‐memory computing and thus would overcome some of the issues concerning the von Neumann bottleneck, which has been intensively investigated. Here, a multi‐bit and functionally complete LIM strategy is designed to efficiently perform multi logical functions in parallel. This strategy is experimentally demonstrated by a multi‐bit ferroelectric tunnel junction (FTJ) memristor with a sub‐nanosecond operation speed which is nearly two orders of magnitude faster than the previous memristive LIM. Using the four resistance states (2‐bit) of only a single FTJ memristor cell, two logical computations are successfully performed in parallel, and the 16 complete Boolean logic functions are implemented within only two steps. In addition, the multi‐encoding schemes are proposed to further improve the efficiency and flexibility of parallel logical computations. Accordingly, the 1‐bit binary full adder can be implemented using as less as three parallel memristors by only performing five steps, and on this basis the N‐bit full adder can also be realized. These results provide a highly efficient LIM approach, which could be a promising candidate for future computing architecture.