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High‐Performance Partially Printed Hybrid CMOS Inverters Based on Indium‐Zinc‐Oxide and Chirality Enriched Carbon Nanotube Thin‐Film Transistors
Author(s) -
Luo Manman,
Xie Huafei,
Wei Miaomiao,
Liang Kun,
Shao Shuangshuang,
Zhao Jianwen,
Gao Tianqi,
Mo Lixin,
Chen Yuan,
Chen Shujhih,
Lee Chiayu,
Cui Zheng
Publication year - 2019
Publication title -
advanced electronic materials
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 2.25
H-Index - 56
ISSN - 2199-160X
DOI - 10.1002/aelm.201900034
Subject(s) - materials science , cmos , noise margin , optoelectronics , transistor , thin film transistor , threshold voltage , carbon nanotube , electronic circuit , nanotechnology , electrical engineering , electronic engineering , voltage , layer (electronics) , engineering
Complementary metal–oxide‐semiconductor (CMOS) inverters with low power consumption and high noise immunity are essential for realizing practical applications of printed logic gates and circuits. However, the performance of existing printed CMOS inverters is still unsatisfactory because p‐type and n‐type transistors do not match well. This work demonstrates novel low‐voltage and high‐performance CMOS inverters using partially printed thin‐film transistors (TFTs) on 50 nm HfO 2 /Si substrates based on n‐type indium zinc oxides (IZOs) and p‐type chirality enriched (9,8) semiconducting single‐walled carbon nanotubes (SWCNTs). The high‐ k dielectric materials grown using atomic layer deposition and (9,8) SWCNTs with relatively large band gaps help to match the characteristics of p‐type and n‐type transistors—the IZO and SWCNT TFTs exhibit similar mobility on/off ratio, small hysteresis, and low sub‐threshold swing at low operating voltages. The hybrid CMOS inverters demonstrate excellent performance with the highest voltage gain up to 45, the largest noise margin of 83% at 1/2 V dd , and the lowest static power consumption of 0.4 µW at V dd of 2 V among recently reported printed CMOS inverters under relatively low annealing temperatures (300 °C). The strategies demonstrated here can be considered as general approaches to realize a new generation of high‐performance printed logic gates and circuits.