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Amorphous‐Si‐Based Resistive Switching Memories with Highly Reduced Electroforming Voltage and Enlarged Memory Window
Author(s) -
Qian Kai,
Nguyen Viet Cuong,
Chen Tupei,
Lee Pooi See
Publication year - 2016
Publication title -
advanced electronic materials
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 2.25
H-Index - 56
ISSN - 2199-160X
DOI - 10.1002/aelm.201500370
Subject(s) - electroforming , materials science , amorphous solid , nanotechnology , optoelectronics , resistive random access memory , non volatile memory , transmission electron microscopy , substrate (aquarium) , electrode , fabrication , voltage , layer (electronics) , electrical engineering , medicine , chemistry , oceanography , alternative medicine , organic chemistry , engineering , pathology , geology
Amorphous Si (a‐Si) based memory devices that offer significant improvement in switching performance are fabricated by inserting a gold nanoparticles (Au NPs) monolayer between the amorphous Si and inert bottom electrodes. It is demonstrated that the Au NPs‐interlayer amorphous Si memory devices deliver great improvements in lowering the electroforming voltage as well as enhancing the ON/OFF ratio, as compared to a pure amorphous Si memory structure. The switching mechanism is due to the modified electric field distribution with the insertion of Au NPs, which can directly affect the dynamic transport of ions and lead to the change of filament growth. Transmission electron microscopy (TEM) is used to directly capture the filaments growth process in these two types of memory devices to verify the evolution of conductive filament (CF). In addition, it is also demonstrated that the Au NPs‐interlay amorphous Si memory fabricated on a flexible substrate can maintain low electroforming voltage and high ON/OFF ratio. This fabrication approach offers a versatile structural platform for next‐generation memory applications with enhancement of the switching properties.