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3D‐Stacked Vertical Channel Nonvolatile Polymer Memory
Author(s) -
Hwang Sun Kak,
Cho Suk Man,
Kim Kang Lib,
Park Cheolmin
Publication year - 2015
Publication title -
advanced electronic materials
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 2.25
H-Index - 56
ISSN - 2199-160X
DOI - 10.1002/aelm.201400042
Subject(s) - materials science , transistor , realization (probability) , layer (electronics) , channel (broadcasting) , non volatile random access memory , milestone , bilayer , ferroelectricity , nanotechnology , computer science , optoelectronics , computer architecture , computer hardware , electrical engineering , semiconductor memory , computer memory , computer network , engineering , voltage , memory refresh , mathematics , membrane , dielectric , history , archaeology , genetics , biology , statistics
A 3D‐stacked one transistor memory with vertically defined submicrometer channels is realized by carefully designing device architecture involving repetitive deposition of layers in combination with a one‐step bilayer transfer of a ferroelectric layer and a semiconducting one. The devices represent a milestone in the realization of mechanically flexible, one‐transistor polymer memory with high memory performance.