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Front‐End‐of‐Line Integration of Graphene Oxide for Graphene‐Based Electrical Platforms
Author(s) -
Lu Xiaoling,
Munief WalidMadhat,
Heib Florian,
Schmitt Michael,
Britz Anette,
Grandthyl Samuel,
Müller Frank,
Neurohr JensUwe,
Jacobs Karin,
Benia Hadj Mohamed,
Lanche Ruben,
Pachauri Vivek,
Hempelmann Rolf,
Ingebrandt Sven
Publication year - 2018
Publication title -
advanced materials technologies
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 2.184
H-Index - 42
ISSN - 2365-709X
DOI - 10.1002/admt.201700318
Subject(s) - graphene , materials science , fabrication , wafer , photolithography , nanotechnology , oxide , microelectronics , graphene oxide paper , graphite oxide , spin coating , optoelectronics , thin film , medicine , alternative medicine , pathology , metallurgy
Scalable and routine integration of chemically exfoliated, graphene‐based materials such as graphene oxide (GO) and reduced graphene oxide (rGO) into standard microelectronic fabrication is a tremendous technological challenge, blocking their advancement toward real applications. A unique approach for wafer‐scale fabrication of rGO devices by a synergistic combination of chemically exfoliated GO with photolithography processing is realized. Using graphite powder as source material, a GO solution is produced in a newly optimized, low‐temperature exfoliation and desalination protocol, resulting in high‐quality GO and confirmed by various characterization techniques. As substrates, 4 in. Si/SiO 2 or glass wafers were first silanized in a well‐controlled, gas‐phase procedure. Large‐area GO thin films are then realized by standard spin‐coating resulting in highly homogeneous, covalently bound layers of controllable thicknesses of 3–7 nm depending on the amount of spin‐coatings. The robust thin films undergo routine photolithography for device fabrication, including reduction via thermal annealing into conductive rGO. The top‐down fabricated rGO devices display high uniformity with electrical resistances varying within only one order of magnitude over wafer‐scale and device yields as high as ≈93% on a wafer. The novel front‐end‐of‐line GO integration protocol offers robust electrical performances for future implementation toward various sensor applications.