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Textured Poling of the Ferroelectric Dielectric Layer for Improved Organic Field‐Effect Transistors
Author(s) -
Laudari Amrit,
Pickett Alec,
ShahedipourSandvik Fatemeh,
Hogan Kasey,
Anthony John E.,
He Xiaoqing,
Guha Suchismita
Publication year - 2019
Publication title -
advanced materials interfaces
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 1.671
H-Index - 65
ISSN - 2196-7350
DOI - 10.1002/admi.201801787
Subject(s) - poling , materials science , pentacene , ferroelectricity , optoelectronics , dielectric , ferroelectric polymers , gate dielectric , field effect transistor , transistor , thin film transistor , layer (electronics) , threshold voltage , organic semiconductor , electric field , organic electronics , composite material , voltage , electrical engineering , engineering , physics , quantum mechanics
Polymer ferroelectrics are playing an increasingly active role in flexible memory application and wearable electronics. The relaxor ferroelectric dielectric, poly(vinylidene fluoride trifluorethylene (PVDF‐TrFE), although vastly used in organic field‐effect transistors (FETs), has issues with gate leakage current especially when the film thickness is below 500 nm. This work demonstrates a novel method of selective poling the dielectric layer. By using solution‐processed 6,13‐bis(triisopropylsilylethynyl)pentacene (TIPS‐pentacene) as the organic semiconductor, it is shown that textured poling of the PVDF‐TrFE layer dramatically improves FET properties compared to unpoled or uniformly poled ferroelectric films. The texturing is achieved by first vertically poling the PVDF‐TrFE film and then laterally poling the dielectric layer close to the gate electrode. TIPS‐pentacene FETs show on/off ratios of 10 5 and hole mobilities of 1 cm 2 Vs −1 under ambient conditions with operating voltages well below −5 V. The electric field distribution in the dielectric layer is simulated by using finite difference time domain methods.