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A Fermi‐Level‐Pinning‐Free 1D Electrical Contact at the Intrinsic 2D MoS 2 –Metal Junction
Author(s) -
Yang Zheng,
Kim Changsik,
Lee Kwang Young,
Lee Myeongjin,
Appalakondaiah Samudrala,
Ra ChangHo,
Watanabe Kenji,
Taniguchi Takashi,
Cho Kyeongjae,
Hwang Euyheon,
Hone James,
Yoo Won Jong
Publication year - 2019
Publication title -
advanced materials
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 10.707
H-Index - 527
eISSN - 1521-4095
pISSN - 0935-9648
DOI - 10.1002/adma.201808231
Subject(s) - materials science , schottky barrier , semiconductor , fermi level , work function , doping , optoelectronics , condensed matter physics , electrical contacts , nanotechnology , electron , physics , diode , layer (electronics) , quantum mechanics
Currently 2D crystals are being studied intensively for use in future nanoelectronics, as conventional semiconductor devices face challenges in high power consumption and short channel effects when scaled to the quantum limit. Toward this end, achieving barrier‐free contact to 2D semiconductors has emerged as a major roadblock. In conventional contacts to bulk metals, the 2D semiconductor Fermi levels become pinned inside the bandgap, deviating from the ideal Schottky–Mott rule and resulting in significant suppression of carrier transport in the device. Here, MoS 2 polarity control is realized without extrinsic doping by employing a 1D elemental metal contact scheme. The use of high‐work‐function palladium (Pd) or gold (Au) enables a high‐quality p‐type dominant contact to intrinsic MoS 2 , realizing Fermi level depinning. Field‐effect transistors (FETs) with Pd edge contact and Au edge contact show high performance with the highest hole mobility reaching 330 and 432 cm 2 V −1 s −1 at 300 K, respectively. The ideal Fermi level alignment allows creation of p‐ and n‐type FETs on the same intrinsic MoS 2 flake using Pd and low‐work‐function molybdenum (Mo) contacts, respectively. This device acts as an efficient inverter, a basic building block for semiconductor integrated circuits, with gain reaching 15 at V D = 5 V.