Layer‐by‐Layer‐Assembled Reduced Graphene Oxide/Gold Nanoparticle Hybrid Double‐Floating‐Gate Structure for Low‐Voltage Flexible Flash Memory | Zendy

Han SuTing | Zendy; Zhou Ye | Zendy; Wang Chundong | Zendy; He Lifang | Zendy; Zhang Wenjun | Zendy; Roy V. A. L. | Zendy

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Layer‐by‐Layer‐Assembled Reduced Graphene Oxide/Gold Nanoparticle Hybrid Double‐Floating‐Gate Structure for Low‐Voltage Flexible Flash Memory

Author(s) -

Han SuTing,

Zhou Ye,

Wang Chundong,

He Lifang,

Zhang Wenjun,

Roy V. A. L.

Publication year - 2013

Publication title -

advanced materials

Language(s) - English

Resource type - Journals

SCImago Journal Rank - 10.707

H-Index - 527

eISSN - 1521-4095

pISSN - 0935-9648

DOI - 10.1002/adma.201203509

Subject(s) - materials science , graphene , non volatile memory , optoelectronics , flash memory , layer (electronics) , transistor , nanotechnology , trapping , monolayer , oxide , nanoparticle , quantum tunnelling , voltage , electrical engineering , computer science , computer hardware , ecology , engineering , metallurgy , biology

A hybrid double‐floating‐gate flexible memory device by utilizing an rGO‐sheet monolayer and a Au NP array as upper and lower floating gates is reported. The rGO buffer layer acts as a charge‐trapping layer and introduces an energy barrier between the Au NP lower floating gate and the channel. The proposed memory device demonstrates a strong improvement in both field‐effect‐transistor (FET) and memory characteristics.

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