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Patterning and Templating for Nanoelectronics
Author(s) -
Galatsis Kosmas,
Wang Kang L.,
Ozkan Mihri,
Ozkan Cengiz S.,
Huang Yu,
Chang Jane P.,
Monbouquette Harold G.,
Chen Yong,
Nealey Paul,
Botros Youssry
Publication year - 2010
Publication title -
advanced materials
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 10.707
H-Index - 527
eISSN - 1521-4095
pISSN - 0935-9648
DOI - 10.1002/adma.200901689
Subject(s) - nanoelectronics , nanotechnology , lithography , cmos , multiple patterning , materials science , transistor , node (physics) , benchmarking , electrical engineering , engineering , optoelectronics , resist , voltage , structural engineering , layer (electronics) , marketing , business
The semiconductor industry will soon be launching 32 nm complementary metal oxide semiconductor (CMOS) technology node using 193 nm lithography patterning technology to fabricate microprocessors with more than 2 billion transistors. To ensure the survival of Moore's law, alternative patterning techniques that offer advantages beyond conventional top‐down patterning are aggressively being explored. It is evident that most alternative patterning techniques may not offer compelling advantages to succeed conventional top‐down lithography for silicon integrated circuits, but alternative approaches may well indeed offer functional advantages in realising next‐generation information processing nanoarchitectures such as those based on cellular, bioinsipired, magnetic dot logic, and crossbar schemes. This paper highlights and evaluates some patterning methods from the Center on Functional Engineered Nano Architectonics in Los Angeles and discusses key benchmarking criteria with respect to CMOS scaling.