Universal Platform for Scalable Semiconductor‐Superconductor Nanowire Networks

Semiconductor‐superconductor hybrids are commonly used in research on topological quantum computation. Traditionally, top‐down approaches involving dry or wet etching are used to define the device geometry. These often aggressive processes risk causing damage to material surfaces, giving rise to scattering sites particularly problematic for quantum applications. Here, a method that maintains the flexibility and scalability of selective area grown nanowire networks while omitting the necessity of etching to create hybrid segments is proposed. Instead, it takes advantage of directional growth methods and uses bottom‐up grown indium phosphide (InP) structures as shadowing objects to obtain selective metal deposition. The ability to lithographically define the position and area of these objects and to grow a predefined height ensures precise control of the shadowed region. The approach by growing indium antimonide nanowire networks with well‐defined aluminium and lead (Pb) islands is demonstrated. Cross‐section cuts of the nanowires reveal a sharp, oxide‐free interface between semiconductor and superconductor. By growing InP structures on both sides of in‐plane nanowires, a combination of platinum and Pb can independently be shadow deposited, enabling a scalable and reproducible in situ device fabrication. The semiconductor‐superconductor nanostructures resulting from this approach are at the forefront of material development for Majorana based experiments.