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Designing Multi‐Level Resistance States in Graphene Ferroelectric Transistors
Author(s) -
Hassanpour Amiri Morteza,
Heidler Jonas,
Müllen Klaus,
Gkoupidenis Paschalis,
Asadi Kamal
Publication year - 2020
Publication title -
advanced functional materials
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 6.069
H-Index - 322
eISSN - 1616-3028
pISSN - 1616-301X
DOI - 10.1002/adfm.202003085
Subject(s) - neuromorphic engineering , materials science , ferroelectricity , transistor , bistability , graphene , non volatile memory , field effect transistor , optoelectronics , nanotechnology , computer data storage , electronic engineering , computer science , electrical engineering , computer hardware , voltage , artificial intelligence , artificial neural network , engineering , dielectric
Conventional memory elements code information in the Boolean “0” and “1” form. Devices that exceed bistability in their resistance are useful as memory for future data storage due to their enhanced memory capacity, and are also a necessity for contemporary applications such as neuromorphic computing. Here, with the aid of an experimentally validated device model, design rules are outlined and more than two stable resistance states in a graphene ferroelectric field‐effect transistor are experimentally demonstrated. The design methodology can be extrapolated for on‐demand introduction of multiple resistance states in ferroelectric transistors for applications both in data storage and neuromorphic computing.